With diversification in mobile communication systems in recent years, carrying out transmission and reception in various methods by use of a single mobile communication terminal has been demanded, and meanwhile, normally, since different mobile communication systems employ different frequency bands, a transmitting and receiving function in multiple frequency bands, a so-called multiband radio function has been required for such a multi-mode terminal.
For a frequency synthesizer used in a multiband radio, it is necessary to be capable of generating local signals in various frequency bands corresponding to the multibands. For example, methods such as GSM (Global System for Mobile Communications) employing a 900 MHz band, DCS (Digital Cellular System) employing a 1800 MHz band, PCS (Personal Communication Services) employing a 1900 MHz band, and UMTS (Universal Mobile Telecommunication System) employing a 2 GHz band have been widely utilized around the world, and development of a four-band radio which can be used for all these frequency bands has been demanded.
In the case of realizing a frequency synthesizer corresponding to such a four-band radio, it is necessary to prepare respective unit synthesizers for GSM transmission, for GSM reception, for DCS transmission, for DCS reception, for PCS transmission, for PCS reception, for UMTS transmission, and for UMTS reception. Since the reception frequency of PCS and transmission frequency of UMTS are almost identical in their bands, both can be used by a single synthesizer, however, this is merely a special case, and basically, unit synthesizers in a number respectively corresponding to necessary multiple frequencies are prepared. Accordingly, if the number of bands increases, the number of unit synthesizers increases in proportion thereto, and hardware results on a huge scale.
As a method for solving such problems, a method of improving an oscillator in modulation sensitivity so as to expand a variable range of the oscillator itself can be considered, however, in this case, there is a problem of fluctuation in frequency of a local oscillator owing to noise and the like from the outside and inside of the chip.
In addition, there is a construction to generate signals having a plurality of frequency bands greater in the number of unit synthesizers by a small-scale circuit configuration provided by combining an arithmetic circuit composed of a frequency divider and a mixer for multiplication with two unit synthesizers. However, this cannot correspond to all the combining communication methods, and there is a drawback in that the number of synthesizers is consequently increased.
Therefore, a method for selecting a voltage controlled oscillator by an external signal according to a desirable oscillation frequency to be obtained has been suggested by use of a plurality of voltage controlled oscillators having different controlled voltage-oscillation frequency characteristics.
In this method, since the plurality of voltage controlled oscillators take charge of mutually different frequency ranges, the frequency range as a whole being wide, although each voltage controlled oscillator has a narrow frequency variable range. Since each voltage controlled oscillator has a narrow frequency variable, each voltage controlled oscillator can take a small modulation sensitivity, which makes it possible to stably operate synthesizers.
FIG. 10 is a diagram showing a configuration example of a quadruple circuit to select from a plurality of voltage controlled oscillators by an external signal and generate a clock.
The present conventional art is, as shown in FIG. 10, a quadruple circuit composed of a PLL circuit having a phase comparator 1, a charge pump 2, a loop filter 3, a voltage controlled oscillator group 4 consisting of four voltage controlled oscillators having different control voltage-oscillation frequency characteristics, a selection circuit 6, a frequency divider 5, an N-channel MOS transistor NM5, and a resistor R. When an output signal S14 from the selection circuit 6 is high in potential (H), the N-channel MOS transistor NM5 is turned on, and by a series connection circuit composed of the resistor R and MOS transistor NM5, current of an output signal S4 from the loop filter 3 is extracted, and potential of a signal S4 line is set to a voltage within a range between reference voltages Vref1 and Vref2, which will be described later (see Japanese Published Unexamined Patent Application No. H09-214335.)
In the following, operations of a quadruple circuit constructed as described above will be described.
The phase comparator 1 generates output signals S1 and S2 based on results of a comparison between a reference signal CK1 and an internal signal CK2. The signal S1 is a signal to indicate a phase lead amount of the reference signal CK1 over the internal signal CK2, the signal S2 is a signal to show a phase lead amount of the internal signal CK2 over the reference signal CK1, and these signals S1 and S2 are inputted into the charge pump 2.
An output signal S3 from the charge pump 2 is inputted into the loop filter 3 and is, after a high-frequency component is removed by the loop filter 3, inputted into the voltage controlled oscillator group 4 as a control voltage S4 of the voltage controlled oscillator group 4.
In the voltage controlled oscillator group 4, signals S10 to S13 generated in the selection circuit 6 are inputted so that one voltage controlled oscillator is selected from the four voltage controlled oscillators of the voltage controlled oscillator group 4. An output signal CK3 from the voltage controlled oscillator group 4 is divided into four by the voltage divider 5 to become an internal signal CK2.
In the conventional art, the circuit locks when operation is performed so that the signal CK1 and signal CK2 coincide in frequency and phase, and a frequency of the signal CK3 obtained from the voltage controlled oscillator group 4 becomes quadruple that of the reference signal CK1.
FIG. 11 is a block diagram showing a configuration of the selection circuit 6 shown in FIG. 10.
When the output signals S10 to S13 from the selection circuit 6 are changed, the output signal S14 becomes high in potential (H) for a fixed time, and thereby, potential of the signal S4 is set so as to be in a range of threshold voltages Vref1 and Vref2 (Vref2>Vref1).
In the selection circuit 6, a voltage comparator 418 having a threshold voltage Vref1 and a voltage comparator 419 having a threshold voltage Vref2 are provided. In the voltage comparator 418, an output signal S15 is set to a high potential (H) when voltage of the inputted control signal S4 is lower than the threshold voltage Vref1, and an output signal S15 is set to a low potential (L) when voltage of the control signal S4 is higher than the threshold voltage Vref1. In addition, in the voltage comparator 419, an output signal S16 is set to a high potential (H) when voltage of the inputted control signal S4 is lower than the threshold voltage Vref2, and an output signal S16 is set to a low voltage (L) when voltage of the control signal S4 is higher than the threshold voltage Vref2.
In addition, a NOR gate 420 for setting a signal S17 to a high potential (H) when the signals S15 and S16 are both low in potential (L) and for, in other cases, setting the same to a low potential (L), an AND gate 421 for setting a signal S18 to a high potential (H) when the signals S15 and S16 are both high in potential (H) and for, in other cases, setting the same to a low potential (L), 2-bit up counters 422 and 423, a subtractor 424 for subtracting an output count value S20 of the counter 423 from an output count value S19 of the counter 422, and a decoder 425 for setting any of only one of the output signals S10 to S13 to a high potential (H) in accordance with a count value S21 inputted from the subtractor 424 are provided.
By the selection circuit 6 having such operation characteristics, from the four voltage controlled oscillators having different control voltage-oscillation frequency characteristics, one voltage controlled oscillator according to a quadruple frequency of the frequency of the reference signal CK1 is automatically selected.
Furthermore, when the selecting state is changed by the selection circuit 6, the signal S14 is temporarily made high in potential (H), and potential of the signal S4 is forcibly set to a value higher than a threshold voltage Vref1 shown in FIG. 12 and also lower than a threshold value Vref2, therefore, outputs from the NOR gate 420 and AND gate 421 are once returned to a low potential (L), whereby in the selecting state of the voltage controlled oscillator group 4 having different control voltage-oscillation frequency characteristics, malfunction can be prevented.
FIG. 12 is a characteristics diagram showing oscillation frequency characteristics, with respect to a voltage of the control signal S4, of the voltage controlled oscillator group 4 shown in FIG. 10. Here, frequencies f1 to f8 have a relationship of f1<f2<f3<f4<f5<f6<f7<f8.
First, description will be given for a case where a desirable oscillation frequency, namely, a quadruple frequency fosc of a frequency of the reference signal CK1 to be inputted into the phase comparator 1 is f1<fosc<f2.
When a lock occurs only at a characteristic D shown in FIG. 12, namely, when voltage of the control signal S4 is not deviated from the range between the threshold voltage Vref1 and threshold voltage Vref2, the output signals S17 and S18 from the NOR gate 420 and AND gate 421 never become high in potential (H), therefore, the counters 422 and 423 never perform a counting operation, and the condition of the output signals S10 to S13 does not change from their initial condition.
In addition, when the characteristic shifts to a characteristic C shown in FIG. 12, further shifts to a characteristic B, and the circuit is finally locked, operations are as follows.
When the control voltage S4 exceeds the threshold voltage Vref2 at the characteristic D, the output signal S17 from the NOR gate 420 becomes high in potential (H), the output value S19 from the counter 422 and an output value S21 from the subtractor 424 are increased by one, whereby, in the decoder 425, only the output signal S13 is switched over from a high-potential (H) condition to a low-potential (L) condition, also only the output signal S12 is switched over from a low-potential (L) condition to a high-potential state (H) condition, and the characteristic shifts to the characteristic C.
At this time of switching over, since the signal S14 temporarily becomes high in potential (H) and the control signal S4 temporarily returns to a voltage in the range between the threshold voltage Vref1 and threshold voltage Vref2, the output signal S17 from the NOR gate 420 changes from a high potential (H) to a low potential (L).
Even after PLL control according to the characteristic C is performed as such, since frequency of the internal signal is still lower than the quadruple frequency of the reference signal, the control voltage S4 again exceeds the threshold voltage Vref2, the selection circuit 6 repeats the aforementioned operations, and the characteristic shifts to the characteristic B. At this point in time, from the voltage controlled oscillator group 4, a frequency roughly the same as that of the reference signal CK1 is being outputted, however, since the phase of the frequency divider 5 does not change in a short time, the phase comparator 1 still operates so as to set the frequency of the internal signal high, and consequently, the control voltage S4 again exceeds the threshold value Vref2, the selection circuit 6 repeats the aforementioned operations, and the characteristic shifts to a characteristic A.
As a result, frequency of the voltage controlled oscillator group 4 becomes higher than that of the reference signal, the phase of the frequency divider 5 has a lead over that of the reference signal, therefore, the control voltage S4 falls below the threshold voltage Vref1, and the characteristic is again shifted to the characteristic B by the selection circuit 6.
Thereafter, the two frequencies are equalized, and a lock finally occurs at the characteristic B.
However, as mentioned above, in a case where a voltage controlled oscillator is selected according to a desirable oscillation frequency by use of a plurality of voltage controlled oscillators having different control voltage-oscillation frequency characteristics, although a broadband PLL circuit can be realized, since, even when a preferred voltage controlled oscillator is selected, the phase of the frequency does not change in a short time, an output from the phase comparator does not sufficiently follow a change in frequency, and consequently, a considerably long time is spent before an optimal oscillator is selected, therein a problem exists.
Since the phase is integration of the frequency, even if an optimal oscillator is selected and an internal signal having a frequency identical to that of the reference signal is inputted into the phase comparator, it takes a great deal of time to bring about an output from the phase comparator into a locked condition, and the output is not immediately brought into a locked condition.